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(R)
STD0550
Matrix Display Digital TV Processor
PRELIMINARY SPECIFICATION
Fully-programmable Digital Video Output Stage for direct RGB interface to Flat Display Panel with 4- to 10bit color resolution and pixel resolution from VGA (640 x 480) to WXGA (1366 x 768) including HDV2.
Video Processing and Display

Versatile Integrated Up-Converter
50/60-Hz Progressive output with Line-Interpolation (A + A*), Field-Merging (A + B) or with Motion-adaptive De-interlacing based on median f(A, B) Advanced Still Picture modes: AA*AA* and ABAB interlaced or AAAA non-interlaced Automatic Movie mode detection and scanning 2 Embedded 32-bit ST20 CPU Cores
Master CPU: 32-bit, 100 MHz, 4 Kbyte Instruction Cache,

3D Temporal Noise Reduction with Comet-effect Correction Scene-change Detector and histogram for Contrast Enhancer Letterbox Format Detection Letterbox and 4:3 to 16:9 format conversion with programmable 5-segment Panoramic mode Picture Structure Improvement including Color Transition Improvement, Luma Peaking/Coring and Luma Contrast Enhancer H/V format conversion with Zoom In/Out (4x to 1/8x) with H/V decimation Very flexible Sync Generator for Master and Slave modes by Vsync and Hsync signals with Line-locked Pixel Clock Mosaic mode with up to 16 pictures displayed Freeze mode
4 Kbyte Data Cache and 8 Kbyte SRAM Slave CPU: 32-bit, 100 MHz, 2 Kbyte Instruction Cache, 2 Kbyte Data Cache and 4 Kbyte SRAM
High-Performance 8-bit Bitmap OSD Generator
Pixel-based resolution with 10-bit RGB outputs Programmable Resolution up to 1920x1024, all standard
Programmable CPU Memory Interfaces for SDRAM, ROM or other peripherals MPEG SDRAM Memory Interface
2 x 16 Mbit or 1 x 64 Mbit or 1 x 128 Mbit SDRAM Up to 133 MHz SDRAM
Hardware Transport Stream Demultiplexor

Parallel/Serial Input DVB Descramblers 32 PID support Support for 2-slot DVB_CI Interface MPEG-1 and MPEG-2 Multi-channel Decoding MP3 Decoding Dolby Digitala (2.0 and 5.1) 3 x 2-channel PCM Outputs (I2S) IEC60958/IEC61937 Digital Output (S/PDIF)
Digital Audio Decoder
displays are supported: - Teletext 1.5 (480x520) and 2.5 (672x520) - Double-page Teletext (960x520) with Picture-and-Text - TeleWeb (640x480) 4 graphic planes with full alpha-blending capabilities: - 24-bit Background Plane - 10-bit RGB Video Plane - Bitmap OSD Plane with Color Map - Up to 128 x 128 pixel Cursor Plane 5th still picture plane available in MPEG video decoder OSD, used for MHP or MHEG-5 applications. 2D Graphics Accelerator
Peripherals and I/Os for TV Chassis Control:

Digital Video Decoder
Supports MPEG-2 MP@ML Fully-programmable Zoom-in and Zoom-out
Multi-Standard Video Encoder for Digital Sources
CVBS, Y/C, RGB and YUV outputs with 10-bit DACs running at
74 fully-programmable I/Os and 4 external interrupts 8-bit programmable PWM with 4 inputs/outputs Infrared Digital Preprocessor Real Time Clock and Watchdog Timer 4 16-bit standard timers 10-bit ADC with 6 inputs and wake-up capability 2 Master/Slave IC Bus Interfaces and UART 2 Smartcard interfaces and Clock Generators Modem support
27 MHz
PAL/NTSC/SECAM Encoding Programmable Luma and Chroma bandwidths Macrovisiona 7.1
Analog-to-Digital Video Multistandard Decoder
Automatic NTSC/PAL/SECAM Digital Chroma Decoder VBI Data Slicer for Teletext, Closed Caption, WSS and other
Teletext 1.5 and 2.5, Closed-Caption, VPS and WSS VBI Data Decoding, TeleWeb Compliant MHP Enhanced Profile and MHEG-5 compliant Embedded Emulation Resources with In-Situ Flash Programming Capabilities Professional Toolset Support
Visual Debugger ANSI C Compiler and Libraries
systems NTSC/PAL Adaptive 4H/2D Comb Filter Analog RGB/Fast Blanking Capture and Insertion in YCrCb Output Flow (SCART legacy) Analog YCrCb inputs with Tint Control Automatic Flesh Control on 117 or 123 Color Axis References NTSC Hue Control Line-locked ITU-R BT. 656/601 YCrCb Outputs (Data and Clock) Orthogonal Correction on Output Pixels ITU-R BT.601 Resolution for all Standards Copy-Protection System compatible

1.8V and 3.3V Power supplies Eco Standby and Low Power modes 27-MHz Crystal Oscillator and VCXO for MPEG decoder Typical Power Consumption: 2.9 Watts 35x35, 532+36 balls PBGA Package
March 2004
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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STD0550
STD0550
Programmable CPU Memory Interface Digital Encoder PAL/NTSC and SECAM Master Controller ST20 32-bit CPU Core
100 MHz 8 Kbytes SRAM 4 Kbytes I-cache 4 Kbytes D-cache Diagnostic Controller Interrupt Controller
External Memory Interface Flash / SDRAM
Video Timebase Generator
MPEG 1&2 Audio Decoder Dolby Digital and MP3
Interrupt Level Controller
3 PCM 1 SPDIF
TV Peripherals UART, RTC ADC, IC Bus I/O Ports WDT, PWM IR Remote Control 2 Smartcards (CI) Modem Support
Clock Generator
HOUT VOUT Output Clock
EMI2 and MPEG SDRAM
EMI1
Sub-picture, OSD & Background
Transport Stream Demultiplexor DVB_CI Control
Video Display Pipeline
Picture Compositor
Standard Definition Input (SDIN)
Front End Interface
H/V Filter and TNR Film Mode Detection
OSD
Slave Controller ST20 32-bit CPU Core
100 MHz 4 Kbytes SRAM 2 Kbytes I-cache 2 Kbytes D-cache Diagnostic Controller Interrupt Controller
Background & Cursor Planes
MPEG 2 Video Decoder
Digital Video Output
Gamma Correction Perfect Color Engine
YSI/CTI
D1: YCRCB[7:0] & Clock
C CVBS1/Y CVBS2/Y
ADC and SRC
Luma/Chroma Separator
Fully Automatic PAL/NTSC/SECAM Decoder Adaptive Luminance Display Data Slicer
Txt, CC, etc.
2D Graphics Accelerator
Transport Stream
4 to 10-bit RGB Digital Video Outputs
Analog Video
R/Cr G B/Cb
Line Format Converter and Output Scaler
ADC
Cr Cb Tint Control
Data Selection and Output Interface
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STD0550 Chapter 1
1.1 1.2
1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Introduction .......................................................................................................................... 4 MPEG Video/Audio Decoder System ................................................................................... 5
MPEG Video Decoder ..........................................................................................................................................6 Digital Audio Decoder ...........................................................................................................................................6 Modem analog front-end interface ........................................................................................................................7 Slave CPU Memory subsystem ............................................................................................................................7 Serial communication ...........................................................................................................................................7 Hardware transport stream demultiplexer interface ..............................................................................................8 On-chip PLL ..........................................................................................................................................................8 Diagnostic controller (DCU) ..................................................................................................................................8 Interrupt subsystem, Slave CPU ...........................................................................................................................8 PAL/NTSC/SECAM encoder .................................................................................................................................9 Smartcard interfaces .............................................................................................................................................9
1.3 1.4
1.4.1 1.4.2 1.4.3
PAL/SECAM/NTSC Analog Video Decoder ......................................................................... 9 Video Display/TV System, Master CPU Controller ............................................................ 10
General Description ............................................................................................................................................10 Deinterlacing Modes and Progressive Scan Output ...........................................................................................11 Regulation Modes ...............................................................................................................................................12
1.5
Software ............................................................................................................................. 13
Chapter 2 Chapter 3 Chapter 4 Chapter 5
5.1
Ball Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Product Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 General Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Package Mechanical Data ............................................................................................... 29
Chapter 6
Summary Of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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STD0550
General Description
1
1.1
General Description
Introduction
The STD0550 is dedicated to iDTV, LCD and Matrix Display. Combined with an external audio processor STV82x7, it provides cost effective high performance solution for LCD-iDTV applications with resolution from VGA (640 x 480) up to WXGA (1366 x 768). It includes an MPEG decoder system, with its slave controller. The Transport stream is demultiplexed and demodulated. The front end interface supports a 2 slot DVB-CI interface. The MPEG slave controller is a ST20, 32 bit CPU, it can access memory via the programmable CPU interface (or EMI) or the shared memory interface (SMI or MPEG SDRAM interface) which is shared with the video, audio and MPEG graphics. PAL/SECAM/NTSC Analog video is demodulated and converted into digital video (4:2:2 YCrCb). Digital video (from a digital or analog source) is sent to the Video display/TV system. Digital audio is sent to the external Audio processor. The video display/TV system is controlled by a Master 32 bit ST20 CPU. The video display system includes field or line-up converter to support progressive display and all peripherals required for controlling the TV chassis. Teletext data is extracted from the incoming stream and decoded by the master CPU. An embedded On-Screen Display (OSD) generator delivers text and graphics. A video display pipeline performs feature box image processing such as picture improvement, horizontal and vertical rescaling and Temporal Noise Reduction. The Master CPU system operates with an external SDRAM that is used for the field-rate upconversion, text and graphic generation.The external SDRAM can be configured as a single bank of 16/64/128 Mb (16-bit configuration) or a dual bank of 16 to 256 Mb (32-bit configuration). Application program codes are stored in an external Flash Memory and executed from the SDRAM.
Figure 1: STD0550 Block Diagram
R Transport Stream Digital Audio Video SDRAM FLASH MPEG Audio/Video Decoder Digital Video Encoder Slave Controller ST20 CPU G D1: YCrCb Video/OSD Display TV System B H/V DE DLCK Master Controller ST20 CPU Multistandard PAL/SECAM/NTSC Analog Video Decoder and Digital Converter D1: YCrCb SDRAM FLASH
Analog Video
STD0550
Digital Audio 3 PCM 1 S/PDIF Analog Audio Amplifier STV82x7
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General Description
STD0550
1.2
MPEG Video/Audio Decoder System
Figure 2: Functional block diagram
2 UART and 2 smartcards IC IR transceiver
Internal peripherals
Reset Test signals
RID TAP Diagnostic controller
Hard reset Test JTAG debugging interface
Low-power control
Central command port
STVD CPU
Debug Block move
MPEG MPEG
QPSK, QAM or COFDM receiver
Front-end and link interface DVB_CI
DMAs
Cache subsystem
Icache Refill control SRAM Dcache CPU arbiter
DMA Communications arbiter External peripherals: Flash, additional DRAM SDRAM Programmable CPU interface (EMI)
ST20 arbiter and memory controller
I/F
SDRAM 2D block move
CD FIFOs
Command interface
16, 32, 64 or 128 Mbit SDRAM
MPEG SDRAM interface
SDRAM arbiter (LMC) clockgen OSD, SP decoder and mixing 3 Video filtering Video decoder Audio decoder VCXO Audio out PCM out S/PDIF
Analog/ digital video output
Digital encoder
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STD0550 1.2.1 MPEG Video Decoder
General Description
This is a real-time video compression processor supporting the MPEG-1 and MPEG-2 standards at video rates up to 720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical and horizontal filters. The MPEG video decoder includes a display unit with five display planes as shown in the figure below. The display planes are normally overlaid in the order illustrated, with the background color at the back and the sub-picture at the front (used as a cursor plane). The sub-picture plane can alternatively be positioned between the OSD and MPEG video planes where it can be used as a second on-screen display plane. The MPEG display unit is used for MHP or MHEG-5 applications.
Figure 3: MPEG display planes
Background color
Subpicture optional positions
Still picture plane
08:23pm
Replay Stats Score Decompressed video 08:23pm 08:23pm Replay Stats Score Replay Stats Score Overlaid planes On-screen display Sub-picture plane
1.2.2
Digital Audio Decoder
The audio decoder supports the decoding of the following formats: Dolby Digital, MPEG-1 layers I, II and III (MP3), MPEG-2 layer II 6 channels, PCMmultichannel linear PCM (LPCM). S/PDIF input data (IEC-60958 or IEC-61937 standards) is accepted if an external circuitry extracts the PCM clock from the stream. Skip frame, repeat blocks and soft mute frame features can be used to synchronize audio and video data. PTS audio extraction is also supported. The device outputs up to 6 channels of PCM data and appropriate clocks for external digital-toanalog converters. Programmable downmix enables 1, 2 or 3 channel outputs. Data can be output in either IS format or Sony format. The decoder can format output data according to IEC-60958 standard (for non compressed data: L/R channels, 16, 18, 20 and 24-bits) or IEC-61937 standard (for compressed data), for FS = 48 kHz, 44.1 kHz or 32 kHz. Sampling frequencies of 48 kHz, 44.1 kHz, 32 kHz and half sampling frequencies are supported. A downsampling filter (48 kHz) is available. The decoder supports dual mode for MPEG and Dolby Digital.
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General Description
STD0550
In global mute mode, the incoming bit-stream is decoded normally but the PCM and S/PDIF outputs are soft-muted. This mode is used to prepare a period of the decoding mode, in order to synchronize audio and video data without hearing the audio. Analog Audio Sources are demodulated using external IC STV82x7. Demodulated digital audio is sent to STV82x7 which also includes Audio processing: virtualizers (SRS TruSurround XT which is Virtual Dolby Digital and Virtual Dolby Surround compliant) and sound enhancements (spatial effects, bass enhancements, dialog enhancement).
1.2.3
Modem analog front-end interface
The modem analog front-end interface is used to transfer transmit and receive DAC and ADC samples between the memory and an external modem analog front-end (MAFE), using a synchronous serial protocol. DMA is used to transfer the sample data between memory buffers and the MAFE interface module, with separate transmit and receive buffers and double buffering of the buffer pointers. FIFOs are used to take into account the access latency to memory, in a worst case system and to allow the use of bursts for memory bandwidth efficiency improvement. V22bis is supported by software.
1.2.4
Slave CPU Memory subsystem
On-chip The on-chip memory includes 2 Kbytes of instruction cache, 2 Kbytes of data cache and 4 Kbytes of SRAM. The subsystem provides 240 Mbytes of internal bandwidth, supporting pipelined 2-cycle internal memory access. The instruction and data caches are direct-mapped, with a write-back system for the data-cache. The caches support burst accesses to the external memories for refill and write-back. Off-chip There are two off-chip memory interfaces: MPEG memory interface controls the movement of data between the STD0550 and 16, 32, 64 or 128 Mbits of SDRAM. This external SDRAM stores the display data generated by the MPEG decoder and the slave CPU working data. The external memory interface (EMI2) accessed by the slave CPU is used for the transfer of data and programs between the STD0550 and external peripherals, flash and additional SDRAM. The EMI uses minimal external support logic for the memory subsystems. It accesses a 32-Mbyte physical address space (greater if SDRAM is used) in four general purpose memory banks of 8 or 16 bits wide, 21 or 22 address lines, and byte select. For applications requiring extra memory, the EMI supports this extra memory with zero external support logic, even for 16bit SDRAM devices. The EMI can be configured for a wide variety of timing and decode functions by the configuration registers. The timing of each of the four memory banks can be set separately, with different device types being placed in each bank with no need for external hardware.
1.2.5
Serial communication
Asynchronous serial controllers The asynchronous serial controller (ASC), also referred to as the UART interface, provides serial communication between the STD0550 and other microcontrollers, microprocessors or external peripherals. The STD0550 has three ASCs available for applications. An additional UART interface is used for the communication between the master CPU and the slave CPU.
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STD0550
General Description
Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. Parity, framing, and overrun error detection increase data transfer reliability. Transmission and reception of data can be double-buffered, or 16-deep FIFOs can be used. A mechanism to distinguish the address from the data bytes is included for multiprocessor communication. Testing is supported by a loop-back option. A 16-bit baud-rate generator provides the ASC with a separate serial clock signal. Two ASCs support full-duplex and 2 half-duplex asynchronous communication, where both the transmitter and the receiver use the same data frame format and the same baud rate. Each ASC can be set to operate in smartcard mode for use when interfacing to a smartcard. Synchronous serial control The two synchronous serial controllers (SSCs) provide high-speed interface to a wide variety of serial memories, remote control receivers and other microcontrollers. They support some features of the serial peripheral interface bus (SPI) and the I2C bus. The SSCs can be programmed to interface to other serial bus standards. They share pins with the parallel input/ output (PIO) ports, and support half-duplex synchronous communication. One SSC supports full-duplex synchronous communication.
1.2.6
Hardware transport stream demultiplexer interface
The STD0550 can be connected to a front-end through the following interfaces: transport stream serial interface, transport stream parallel interface. The PIO pins can be tri-stated under software control to support low cost DVB-CI implementations and similar module interfaces.
1.2.7
On-chip PLL
There are three on-chip frequency synthesizers and one PLL, accepting 27 or 54 MHz input, which generate all the internal high-frequency clocks needed for the slave CPU, MPEG and audio subsystems.
1.2.8
Diagnostic controller (DCU)
The ST20 diagnostic controller unit (DCU) is used to boot the CPU and to control and monitor the chip systems via the standard IEEE 1194.1 test access port. The DCU includes on-chip hardware with ICE (in-circuit emulation) and LSA (logic state analyzer) features to facilitate verification and debugging of software running on the on-chip CPU in real time. It is an independent hardware module with a private link from the host to support real-time diagnostics. The slave CPU and master CPU each have their own DCU.
1.2.9
Interrupt subsystem, Slave CPU
The interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so that an interrupt handling process can be run. An interrupt can be signalled by one of the following: a signal on an external interrupt pin, a signal from an internal peripheral or subsystem, software asserting an interrupt in the pending register. Interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt-level controller. The interrupt controller supports eight prioritized interrupts as inputs and manages the pending interrupts. This allows the nesting of preemptive interrupts for real-time system design. Each interrupt can be programmed to be at a lower or higher priority than the high priority process queue.
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General Description 1.2.10 PAL/NTSC/SECAM encoder
STD0550
The integrated digital encoder converts a multiplexed 4:2:2 or 4:4:4 YCbCr stream into a standard analog baseband PAL/NTSC or SECAM signal and into RGB, YUV, YC and CVBS components. The encoder can perform closed-caption, CGMS encoding, and allows MacrovisionTM 7.1 copy protection (option). The digital encoder is able to encode Teletext according to the CCIR/ITU-R Broadcast Teletext System B specification, also known as World System Teletext. In DVB applications, Teletext data is embedded within DVB streams as MPEG data packets. It is the responsibility of the software to handle incoming data packets and in particular to store Teletext packets in a buffer, which then passes them to the digital encoder on request. The digital encoder also provides enhanced possibilities through programmable luma and chroma bandwidth.
1.2.11 Smartcard interfaces
Two smartcard interfaces support smartcards compliant with ISO7816-3. Each interface has a UART (ASC), a dedicated programmable clock generator, and eight bits of parallel IO port.
1.3
PAL/SECAM/NTSC Analog Video Decoder
The STD0550 includes a high-quality video front-end for processing all analog standards into a digitalized 4:2:2 YCrCb video format. It processes NTSC/PAL/SECAM CVBS signals, as well as conventional analog RGB or YCrCb signals. The analog video decoder outputs demodulated chrominance, in-phased luminance and sliced data for the most common services such as Teletext, Closed Caption, WSS, etc. The analog video decoder does not need an external synchronization system. It extracts all necessary synchronization signals from CVBS or Y signals, and delivers the horizontal, vertical and frame signals either on dedicated pins or embedded into the digital bit stream. It features automatic standard recognition and automatic selection of the optimal Y/C separation algorithm according to the standard and has extensive output scaling capabilities. The analog video decoder chip includes an analog RGB capture feature and programmable automatic mixing with the main picture digital output. 8-bit ITU-R BT.601/656 output standard is supported.
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STD0550
General Description
All sub-level blocks operate at the frequency used as a sampling frequency (fS) for the five embedded A/D converters. This free-running clock is called the system clock (fS) and is provided by an external clock generator from a video display/TV system.
Figure 4: Architectural Block Diagram
CVBS1/Y CVBS2/Y C
Analog Input Stage
R/Cr G B/Cb FB
Input SRC
Luma Chroma Separator
Standard Identifier & Chroma Demodulator
PAL/NTSC/SECAM
Soft Mixer
RGB Insertion
Format Converter & Output Scaler
Video Correction
IC Interface System Clock Generation
Synchronization and Monitoring Unit Output FIFO VBI Slicer
Line-locked Output Pixel Clock
YCrCb[7:0] HSYNC VSYNC Field Line-locked Output Pixel Clock
1.4
1.4.1
Video Display/TV System, Master CPU Controller
General Description
The STD0550 includes a 32-bit ST20 CPU core with all peripherals required for controlling the TV chassis. Teletext data is extracted from the incoming stream and decoded by the CPU. An embedded On-Screen Display (OSD) generator delivers the text and graphics. The Video Display Pipeline performs feature box image processing such as picture improvement, horizontal and vertical rescaling and Temporal Noise Reduction.
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General Description
STD0550
The video display/TV system operates with a single external SDRAM that is used for the field-rate up-conversion, text and graphic generations.The external SDRAM can be configured as a single bank of 16/64/128 Mb (16-bit configuration) or a dual bank of 16 to 256 Mb (32-bit configuration). Application program codes are stored in an external Flash memory and executed from the SDRAM.
Figure 5: Architectural Block Diagram
NRESET
Build-Up Counter
Video Pipeline YSI CTI OSD Pipeline
Picture Compositor Comp. Cursor BG Plane Fast Blanking CSA
8 YCRCB[7:0] CLK_DATA HSYNC VSYNC
HV Filter TNR SDIN Block
Digital Video Output Communiction Perfect Color Engine
4 to 10 bits R 4 to 10 bits G 4 to 10 bits B H/V DE DLCK SDRAM
EMI4 2D Block Move 16/32 Flash Time Base Generator 30 Hout Vout
ST20 Core
27 MHz Crystal
Clock Generator
TV Peripherals TV Chassis Control
CLKXTM
CLKXTP
CLK_DFL
I/Os
1.4.2
Deinterlacing Modes and Progressive Scan Output
The de-interlacing can be done in the following modes:

Spatial line interpolation, using the high resolution vertical polyphase filter Motion adaptive spatial-temporal interpolation, using the median filter Field merging for film sources
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STD0550
General Description
The following table shows typical de-interlacing modes, according to the input format:
Table 1: De-interlacing and Scaling Modes
INPUT Panels & Output modes 50 Hz interlaced Video
A+A*B*+B Or A+Med (A,B)
50 Hz interlaced movie
A+B Z out H 720>640 Z out V 576>480
50 Hz n-interlaced game
A+A*B*+B Or A+Med (A,B) Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B) Zin H 720>1024 Z in V 576>768
60 Hz interlaced Video
A+A*B*+B Or A+Med (A,B) Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B) Zin H 720>1024 Z in V 576>768
60 Hz interlaced movie (3:2)
3:2pd Z out H 720>640 Z out V 576>480
60 Hz interlaced movie (2:2)
A+B Z out H 720>640 Z out V 576>480
60 Hz n-interlaced game
A+A*B*+B Or A+Med (A,B) Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B) Zin H720>1024 Z in V 576>768
VGA
OUTPUT
Z out H 720>640 Z out V 576>480 A+A*B*+B Or A+Med (A,B)
A+B Z in H 720>1024 Z in V 576>768
3:2pd Zin H 720>1024 Z in V 576>768
A+B Zin H 720>1024 Z in V 576>768
XGA
Z in H 720>1024 Z in V 576>768
Note:
720 pixels/line refers to ITU-R BT 601/656 video input standard resolution.
1.4.3
Regulation Modes
The regulation modes of the input and output dataflows are based on the configurations of several blocks such as the SDIN, VTG, Display, and also depends on the selected synchronization modes. These regulation modes are then managed by a software layer that controls the various registers and includes algorithms to maintain the balance between the input and output dataflows. This service software layer allows various regulation modes as described below, selectable at the application level. When the VTG block is set in Slave mode, the PLL that line-locks the clock pixel to the Hsync signal is used to regulate the input and output dataflows. When the VTG block is set in Master mode, the following regulation modes are possible: 1. Frame Skip & Repeat Mode (used for Proscan mode) In this mode, depending on the speed variations between the input flow and the output flow, a frame is repeated or skipped from time to time (1 to 2 per second). 2. Field Skip & Repeat Mode (used for field rate up-conversion as 100 Hz) In this mode, depending on the speed variations between the input flow and the output flow, a field is repeated or skipped from time to time (1 to 2 per second). 3. Line Skip & Repeat Mode In this mode, certain lines are repeated or skipped during the VBI, depending on the delay between the input and output Vsync signals. 4. Pixel Skip & Repeat Mode In this mode; pixel periods are repeated or skipped during the horizontal or vertical blanking interval, depending on the delay between each Vsync signal. 5. Clock Modulation Mode
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General Description
STD0550
In this mode, the output pixel clock free-running frequency is fine-tuned, depending on the delay between the input and output Vsync signals. The PLL filtering is performed by software.
1.5
Software
The layering model adopted for the Software Stack is based on certain non-functional requirements:

Re-usable Portable Modular Reliable and robust Readable and maintainable
Figure 6: Global Software Architecture
Real-Time Embedded Operating System
Application Level Chassis Control Services
Graphics, Remote Control, Zapper
Decoders
Drivers
IC, OSD, SDIN, Audio, Video
STD0550
The application software consists of 4 main layers based on these non-functional requirements:
System Layer provides certain general-purpose components such as Handle or Link List Managers. This layer also contains the Operating System Abstraction Layer (OSAL) components which enable other layers to be OS-independent. Driver Layer provides a hardware abstraction to the upper layers making them hardwareindependent. Service Layer contains the components that provide the Application layer with high level interfaces in order to manage the TV set. The set of Service components included in the demonstration application are very useful for developing applications.
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STD0550
General Description
Application Layer which contains the software that defines the "Look & Feel" of the TV set. This layer, for instance, contains the components that are responsible for the following features: interpretation of user inputs, display and navigation functions and Teletext applications.
Figure 7: Software Architecture Example
STV API Chassis Control Audio Video Switch STV2310 Tuner Switch Install Teletext Channel Select Keyboard Infrared Audio Electronic Program Guide Graphics Data Server VTG Video TeleWeb User Input H/V & SRC GAMMA MHP/MHEG-5
User Interface Resident Applications
OS Toolkit
C.A DSM_CC Table Services Server Transport Stream MPEG Video Digital Audio
OSD
SDIN
IC
Drivers
CI
Hardware Layer
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Ball Connections
STD0550
2
Ball Connections
Alternate functions printed in Italic show a suggested use of the PIO; alternate functions not printed in Italic are multiplexed with a specific hardware.
Table 2: Pins sorted by function Alternate Function Ball Ball Name Main Function Input Output
EXT_AUD_CLK EXT_AUD_DATA EXT_AUD_REQ O O I/O O I/O EXT_AUD_WCLK O O PWR PWR I PWR PWR I UART0_DATA (SC0_DATA) TTX_IN_CLOCK SC0_CLOCK SC0_RST SC0_CMD_VCC SC0_DATA_DIR/ DVB_OE SC0_DETECT SSC0_CLOCK SC external clock PARA_DVALID UART2_RXD PARA_SYNC UART1_TXD DVB_WE UART3_DATA (SC1_DATA) OSD_ACTIVE DVB_IOWR DVB_IORD SSC0_DATA (MTSROUT/MRSTIN) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Type
Audio DAC (Digital Decoder) D24 C26 C25 C24 B26 B25 A26 H22, J22 D25 P3 E19 P14 N23 D3 Y2 G1 V3 W3 Y1 F1 G3 U1 U2 G4 DAC_SCLK DAC_PCMOUT0 DAC_PCMOUT1 DAC_PCMOUT2 DAC_PCMCLK DAC_LRCLK SPDIF_OUT VDD_PCM VSS_PCM RESET VDD_PLL VSS_PLL PIX _CLK PIO0[0] PIO0[1] PIO0[2] PIO0[3] PIO0[4] PIO0[5] PIO0[6] PIO0[7] PIO1[0] PIO1[1] PIO1[2] Oversampling clock PCM_OUT0 PCM_OUT1 PCM_OUT2 PCM_CLOCK Left/right clock SPDIF_OUT VDD frequency synthesizer: 1.8 V VSS frequency synthesizer: GND Chip reset VDD PLL = 1.8 V GND PLL = GND 27MHz main clock PIO0[0] PIO0[1] PIO0[2] PIO0[3] PIO0[4] PIO0[5] PIO0[6] PIO0[7] PIO1[0] PIO1[1] PIO1[2]
Clock and Reset (Digital Decoder)
PIOs and Communication (Digital Decoder - Slave CPU)
U3 T3 W2 T1 G2 H3
PIO1[3] PIO1[4] PIO1[5] TRIGGER_IN TRIGGER_OUT PIO2[0]
PIO1[3] PIO1[4] PIO1[5] Trigger in for DCU Trigger out for DCU PIO2[0]
UART2_TXD
I/O I/O I/O I/O I/O I/O O
15/32
STD0550
Table 2: Pins sorted by function
Ball Connections
Alternate Function Ball
W1 H4 H2 H1 F4 F2 L25 K4 K2 K1 L3 L4 L2 L1
Ball Name
PIO2[1] PIO2[2] PIO2[3] PIO2[4] PIO2[5] PIO2[6] PIO2[7] PIO3[0] PIO3[1] PIO3[2] PIO3[3] PIO3[4] PIO3[5] PIO3[6] PIO2[1] PIO2[2] PIO2[3] PIO2[4] PIO2[5] PIO2[6] PIO2[7] PIO3[0] PIO3[1] PIO3[2] PIO3[3] PIO3[4] PIO3[5] PIO3[6]
Main Function Input
UART1_RXD PARA_STROBE
Type Output
MAFEIF_DOUT PARA_REQ MAFEIF_HC1 SC1_CLOCK SC1_RST SC1_CMD_VCC SC1_DATA_DIR SC1_DETECT/ CFC MAFEIF_SCLK PARA_DATA{0] MAFEIF_DIN PARA_DATA[1] MAFEIF_FSI PARA_DATA[2] CAPTURE_IN0 PARA_DATA[3] CAPTURE_IN1 PARA_DATA[4] CAPTURE_IN2 PARA_DATA[5] PARA_DATA[6] UART1 CTS (CTS1) PARA_DATA[7] UART2 CTS (CTS2) UART1 RTS (RTS1) UART2 RTS (RTS2) COMP_OUT1 YC_CLKOUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
M3
PIO3[7]
PIO3[7]
COMP_OUT0
I/O
E25, F23, F24, H23, H24, H25, K23, K25 PIO4[0:7] V1 V2 J3 M25 M26 PIO5[0] PIO5[1] PIO5[2] PIO5[3]1 PIO5[4] PIO4[0:7] PIO5[0] PIO5[1] PIO5[2] PIO5[3] PIO5[4] B_WCLK SSC1_DATA B_V4 SSC1_CLOCK IRB_IR input IRB_UHF input IRB_drivePPMsign al IRB_drive0orZ1 (jack) OSC_IN_CLK Auxiliary Clock (Digital Decoder) T2 AUXCLK Auxiliary clock O I/O I/O I/O I/O YC[0:7]/NCO[0:7] I/O I/O
N26
PIO5[5]
PIO5[5]
I/O
16/32
Ball Connections
Table 2: Pins sorted by function Alternate Function Ball Ball Name Main Function Input
EMI Interface (Digital Decoder - Slave CPU) C13, D13, B13, A13, C8, A7, B7, D7, C7, A6 CPU_ADR[1:10] CPU_ADR[11:21] D10, C10, A9, B9, D9, C9, A8, B8 CPU_DATA[0:7] D5, C5, B2, A2, A3, C4, B4, A4 CPU_DATA[8:15] F3 CPU_RAS1 DATA[8:15] DRAM RAS DATA[0:7] ADR[1:10] ADR[11:21]
STD0550
Type Output
O O I/O I/O NOT_SDRAM_CS 1/ CHIPSEL. BANK3 NOT_SDRAM_WE DQM[0] DQM[1] SDRAM_CAS/ CPU_ADR[22] NOT_SDRAM_CS 0 SDRAM_RAS/ NOTCHIPSELBAN K0 I/O
B12, B6, D6, C3, C12, D12, A1, D1, D2, C2, C1
E1 C11 A10 B5 D11 A11 B11
CPU_WAIT CPU_RW CPU_BE[0] CPU_BE[1] CPU_CAS0 CPU_CAS1 CPU_CE[0]
Wait state Read not write Byte 0 enable Byte 1 enable DRAM CAS0 DRAM DRAM_RAS0
I O O O O O O
E4 E2 E3 A5 B1 J2 J1 K3 Timers M24 L23 M23 R4 R2 R1 R3 P4
CPU_CE[1] CPU_CE[2] CPU_CE[3] CPU_PROCLK CPU_OE IRQ[0] IRQ[1] IRQ[2] PWM0 PWM1 PWM2 TCK TDI TDO TMS TRST
2
Chip select bank 1 Chip select bank 2 Chip select bank 3 EMI clock Output enable IRQ[0] (SERVO_IRQ) IRQ[1] IRQ[2] (MD_IRQ) Pulse width modula 0 Pulse width modula 1 Pulse width modula 2 Test clock Test data in Test data out Test mode select Test reset HSYNC BOOTFROMRO M VSYNC/ODDEVEN CS_SUB_BANK3
O O O O I/O I I I O O O I I O I I
Interrupt (Digital Decoder - Slave CPU)
JTAG (Digital Decoder - Slave CPU)
Front-end (Digital Decoder) M4 B_DATA IS data FEC_DATA I
17/32
STD0550
Table 2: Pins sorted by function
Ball Connections
Alternate Function Ball
M2 M1 N3 T26 T25 T23 R25 R26 P24 R23 R24 P25 P23 K22 P26 L22 M13
Ball Name
B_BCLK B_FLAG B_SYNC R_OUT G_OUT B_OUT Y_OUT C_OUT CV_OUT I_REF_RGB V_REF_RGB I_REF_YCC V_REF_YCC VDD_RGB VSS_RGB VDD_YCC VSS_YCC
Main Function Input
IS bit clock IS error flag IS sector/ABS time R_OUT G_OUT B_OUT Y_OUT C_OUT CV_OUT RGB DAC ref. current RGB DAC ref. voltage YCC DAC ref. current YCC DAC ref. voltage VDDA_RGB: 3.3 V VSSA_RGB: GND VDDA_YCC: 3.3 V VSSA_YCC: GND FEC_B_CLK FEC_P_CLK FEC_ERROR
Type Output
I I I O O O O O O I I I I PWR PWR PWR PWR
Video DAC (Digital Decoder)
Shared Memory Interface (Digital Decoder) C23, A24, B24, A25 SMI_ADR[0:3] C18, D18, B18, D17, A18, B17 SMI_ADR[4:9] B23, A17, C22, A23 SMI_ADR [10:13] SMI_DATA[0:15] D22, D23 A19 B19 D19 C19, A14 D16 C16 U25 U26 SMI_CS[0:1] SMI_RAS SMI_CAS SMI_WE SMI_DQML, U SMI_CLKIN SMI_CLKOUT CVBS2_Y C Address bus SDRAM Data bus SDRAM Chip select bank 0,1 RAS SDRAM CAS SDRAM SDRAM write enable DQ mask enable low, up SDRAM clock in SDRAM clock out CVBS or Y Input 2 (Selected by programming) Chroma Input (Y/C inputs used for S-Video) (Selected by programming) Fast Blanking Input (To be used only when R_CR, G, and B_CB inputs are connected) O I/O O O O O O I O I I A22, C21, D21, B21, A21, C20, D20, B20, B14, D14, C14, B15, D15, C15, A16, B16 Address bus SDRAM O Address bus SDRAM O
Analog Pins (Analog Decoder)
W23
FB
I
18/32
Ball Connections
Table 2: Pins sorted by function Alternate Function Ball
AA19 AB19 W25 W26 V24 W26
STD0550
Ball Name
REFP_RGB REFM_RGB R_CR G B_CB ADCIN
Main Function Input
Positive Reference Voltage for RGB ADCs Negative Reference Voltage for RGB ADCs R Input for RGB Insertion. Cr Input for Analog YCrCb mode. G Input for RGB Insertion. B Input for RGB Insertion. Cb Input for Analog YCrCb mode. CVBS ADC Input (To be connected to Anti-Aliasing Filter output) CVBS Anti-Aliasing Filter Reference Voltage Video Analog Front-end Multiplexer Output for external filtering Positive Reference Voltage for CVBS and Chroma ADCs Negative Reference Voltage for CVBS and Chroma ADCs connected to GND CVBS or Y Input 1 (Selected by programming) Digital Video Output 7 Digital Video Output 6 Digital Video Output 5 Digital Video Output 4 Digital Video Output 3 Digital Video Output 2 Digital Video Output 1 Digital Video Output 0 Output Pixel Clock
3
Type Output
REF REF I I I I
V25 V26
VIDEOCOMM VIDEO_OUT
REF O
U21 U20
REFP_CVBS REFM_CVBS
REF GND
U24
CVBS1_Y
I
Digital Output (Analog Decoder) J26 J24 G26 G25 J23 F26 E24 D26 L26 AC3 YCRCB7 YCRCB6 YCRCB5 YCRCB4 YCRCB3 YCRCB2 YCRCB1 YCRCB0 CLK_DATA PLLLOCK O O O O O O O O O O
Output PLL Lock Signal Alternate Function: PIO[0] Bus extension Horizontal Synchronization Pulse Output Alternate Function: PIO[1] Bus extension Vertical Synchronization Pulse Output Alternate Function: PIO[2] Bus extension Field (Parity) Output Signal Alternate Function: PIO[3] Bus extension
AB26
HSYNC
O
AA26
VSYNC
O
N25
FIELD
O
19/32
STD0550
Table 2: Pins sorted by function
Ball Connections
Alternate Function Ball Ball Name Main Function Input
Clock Signal Pins (analog decoder) AA22 AA23 XTALOUT XTALIN_CLKXTP Crystal Pad Oscillator Output Crystal Pad Oscillator Input Alternate Function: Differential Clock input Y23 CLKXTM Differential Clock input (To be used in conjunction with CLKXTP) Test Mode (Must be tied low in Normal mode) IC Bus Data IC Bus Clock Hardware Reset (Active low) IC Address Selection (Must be tied high or low according to selected IC address). 0: 86h/87h 1: 8Eh/8Fh Y25 CLKSEL Input Clock Selection (Must be coherent with XTALIN_CLKXTP and CLKXTM connections) 0: CLKXTP and CLKXTM 1: XTAL D1 Standard Definition Digital Video Input Stage N24 L24 K26 E26 E23 F25 G23 G24 H26 K24 J25 VSYNC HSYNC CLK_DATA YCRCB0 YCRCB1 YCRCB2 YCRCB3 YCRCB4 YCRCB5 YCRCB6 YCRCB7 Vertical Sync Input Horizontal Sync Input Video Input Clock 4:2:2 Data Stream Input 0 4:2:2 Data Stream Input 1 4:2:2 Data Stream Input 2 4:2:2 Data Stream Input 3 4:2:2 Data Stream Input 4 4:2:2 Data Stream Input 5 4:2:2 Data Stream Input 6 4:2:2 Data Stream Input 7 I I I I I I I I I I I I I O I
Type Output
Configuration Pins (analog decoder) Y22 AB3 AA3 AB22 W22 TST_MODE SDA SCL NRESET I2CADD I I/O I/O I I
Digital Video Output Stage Synchro Output and Clock Output AD6 AC6 AE6 K5 L5 M5 N5 Vout Hout CLK_DFL P_VIDEO0 P_VIDEO1 P_VIDEO2 P_VIDEO3 Vertical Sync Output Horizontal Sync Output Clock Output for Video/Scan Processor Digital Video Output 0 Digital Video Output 1 Digital Video Output 2 Digital Video Output 3 O O O O O O O
20/32
Ball Connections
Table 2: Pins sorted by function Alternate Function Ball
P5 R5 T5 U5 V5 W5 Y4 Y5 AA5 AB4 AB5 AC5 AD5 AE5 AF5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AE4 AF4 AC1 AC4 AD9 AC9 T4 U4 W4 V4 AE3 AD3 AF2 AE2 AD2 AF1
STD0550
Ball Name
P_VIDEO4 P_VIDEO5 P_VIDEO6 P_VIDEO7 P_VIDEO8 P_VIDEO9 P_VIDEO10 P_VIDEO11 P_VIDEO12 P_VIDEO13 P_VIDEO14 P_VIDEO15 P_VIDEO16 P_VIDEO17 P_VIDEO18 P_VIDEO19 P_VIDEO20 P_VIDEO21 P_VIDEO22 P_VIDEO23 P_VIDEO24 P_VIDEO25 P_VIDEO26 P_VIDEO27 P_VIDEO28 P_VIDEO29 DCLK DE PORTA0 PORTA1 PORTA2 PORTA3 PORTA4 PORTA5 PORTA6 PORTA7 PORTB0 PORTB1 PORTB2 PORTB3 PORTB4 PORTB5
Main Function Input
Digital Video Output 4 Digital Video Output 5 Digital Video Output 6 Digital Video Output 7 Digital Video Output 8 Digital Video Output 9 Digital Video Output 10 Digital Video Output 11 Digital Video Output 12 Digital Video Output 13 Digital Video Output 14 Digital Video Output 15 Digital Video Output 16 Digital Video Output 17 Digital Video Output 18 Digital Video Output 19 Digital Video Output 20 Digital Video Output 21 Digital Video Output 22 Digital Video Output 23 Digital Video Output 24 Digital Video Output 25 Digital Video Output 26 Digital Video Output 27 Digital Video Output 28 Digital Video Output 29 Digital CMOS Clock Digital CMOS Data Enable Port A0 Port A1 Port A2 Port A3 Port A4 Port A5 Port A6 Port A7 Port B0 Port B1 Port B2 Port B3 Port B4 Port B5
Type Output
O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Parallel Input/Output Pins, Master CPU Control
21/32
STD0550
Table 2: Pins sorted by function
Ball Connections
Alternate Function Ball
AB2 AB1 AA4 AA2 AE7 AC7 AD7 AF6 AF7 AD8 AC8 AE8 AC2 AF3 AF8 AD1
Ball Name
PORTC0 PORTC1 PORTC2 PORTC3 PORTC4 PORTC5 PORTC6 PORTC7 PORTD0 PORTD1 PORTD2 PORTD3 PORTD4 PORTD5 PORTD6 PORTD7 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 Port C6 Port C7 Port D0 Port D1 Port D2 Port D3 Port D4 Port D5 Port D6 Port D7
Main Function Input Output
Type
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
External Memory Interface, Master CPU Flash Data Bus, Master CPU AE26 AF26 AD25 AE25 AF25 AD24 AE24 AF24 AF22 AD21 AC21 AE21 AF21 AD20 AC20 AE20 AF20 AD19 AE19 AF19 AD18 AC18 AE18 AF18 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15 SDRAM_D0 SDRAM_D1 SDRAM_D2 SDRAM_D3 SDRAM_D4 SDRAM_D5 SDRAM_D6 SDRAM_D7 Flash Data Bus 0 Flash Data Bus 1 Flash Data Bus 2 Flash Data Bus 3 Flash Data Bus 4 Flash Data Bus 5 Flash Data Bus 6 Flash Data Bus 7 Flash Data Bus 8 Flash Data Bus 9 Flash Data Bus 10 Flash Data Bus 11 Flash Data Bus 12 Flash Data Bus 13 Flash Data Bus 14 Flash Data Bus 15 SDRAM Data Bus 0 SDRAM Data Bus 1 SDRAM Data Bus 2 SDRAM Data Bus 3 SDRAM Data Bus 4 SDRAM Data Bus 5 SDRAM Data Bus 6 SDRAM Data Bus 7 I I I I I I I I I I I I I I I I I I I I I I I I
SDRAM Data Bus, Master CPU
22/32
Ball Connections
Table 2: Pins sorted by function Alternate Function Ball
AE11 AC11 AD11 AF10 AE10 AC10 AD10 AF9 AF17 AE17 AC17 AD17 AF11 AD12 AC12 AE12 AD13 AC13 AD16 AE13 AF13 AF23 AC22 AF16 AC16 AE23 AD23 AE22 Controls AF15 AC23 AD15 AC15 AE15 AD14 AC14 AE14 AF14 P1 RD_NOTWR NOT_CS_FLASH NOT_CS_SDRAM NOT_RAS NOT_CAS NOT_BE0 NOT_BE1 CKOUT_SDRAM CKIN_SDRAM XTALIN SDRAM Write Enable / Flash Write Enable* Flash Chip Select SDRAM Chip Select SDRAM Row Address Strobe SDRAM Column Address Strobe / Flash Output Enable* SDRAM Byte Enable 0 SDRAM Byte Enable 1 Clock Output for SDRAM SDRAM Clock Feedback 27 MHz Crystal Input
STD0550
Ball Name
SDRAM_D8 SDRAM_D9 SDRAM_D10 SDRAM_D11 SDRAM_D12 SDRAM_D13 SDRAM_D14 SDRAM_D15 ADDR_0 ADDR_1 ADDR_2 ADDR_3 ADDR_4 ADDR_5 ADDR_6 ADDR_7 ADDR_8 ADDR_9 ADDR_10 ADDR_11 ADDR_12 ADDR_13 ADDR_14 ADDR_15 ADDR_16 ADDR_17 ADDR_18 ADDR_19
Main Function Input
SDRAM Data Bus 8 SDRAM Data Bus 9 SDRAM Data Bus 10 SDRAM Data Bus 11 SDRAM Data Bus 12 SDRAM Data Bus 13 SDRAM Data Bus 14 SDRAM Data Bus 15 Address Bus 0 Address Bus 1 Address Bus 2 Address Bus 3 Address Bus 4 Address Bus 5 Address Bus 6 Address Bus 7 Address Bus 8 Address Bus 9 Address Bus 10 Address Bus 11 Address Bus 12 Address Bus 13 Address Bus 14 Address Bus 15 / BA0 Address Bus 16 / BA1 Address Bus 17 Address Bus 18 / Not_BE2 Address Bus 19 / Not_BE3
Type Output
I I I I I I I I 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 27 MHz I n/a
EMI Address Bus, Master CPU
Master CPU System Controls
23/32
STD0550
Table 2: Pins sorted by function
Ball Connections
Alternate Function Ball
N2 Y24 AA24 N4 AB23 AB24 AC26 AB25 AC24 AC25
Ball Name
XTALOUT CLKXTM CLKXTP SHIELD_PLL TCK TDI TDO TMS TRST NRESET
Main Function Input
27 MHz Crystal Output 27 MHz Differential Clock for STV2310 27 MHz Differential Clock for STV2310 To connect to Analog Ground Supply for PLL Test Clock Input Test Data Input Test Data Output Test Mode Select Input Test Reset Input Master CPU System Reset Input (Active Low)
Type Output
n/a 0V 1.8V GND I I Hi-Z I I I
Power Supply (Digital Decoder) E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, F5, G5, H5, J5 VDD3_3 3.3 V power supply for Digital Decoder 1.8 V power supply for Digital Decoder 1.8 V Analog Voltage Supply for Analog Input Stage (Analog Decoder) Analog Ground Supply (Substrate Polarization) (Analog Decoder) 1.8 V Analog Voltage Supply (Output and Pin Isolation layer) (Analog Decoder) 1.8 V Analog Voltage Supply for Clock Generator (Analog Decoder) Analog Ground Supply for Clock Generator (Analog Decoder) Guard Ring (Analog Input Stage) To be connected to Analog Ground Supply (Analog Decoder) 1.8 V Analog Voltage Supply (RGB) (Analog Decoder) Analog Ground Supply (RGB) (Analog Decoder) 1.8 V Analog Voltage Supply (Analog Input Stage) (Analog Decoder) Analog Ground Supply (Analog Input Stage) (Analog Decoder) Analog Ground Supply (Analog Input Stage) (Analog Decoder) PWR
E15, E16, E17, E18, E20, E21, E22, G22, F22 VDD1_8 Power Supply (Analog Decoder) T21, R21, P21 C6 AA16, AA17 AA18 VCC18_CVBS PWR PWR
GNDSUB VCC18SUB
PWR PWR
VCC18_CLK
PWR
D25 D4
GND_CLK SHIELD
PWR PWR
T21 J4 T21
VCC18_RGB GND_RGB VCC18_DIG
PWR PWR PWR
L13 L14
GND_DIG GND_IO
PWR PWR
24/32
Ball Connections
Table 2: Pins sorted by function Alternate Function Ball
V21
STD0550
Ball Name
VCC33_IO
Main Function Input
3.3 V Analog Voltage Supply (Analog Input Stage) (Analog Decoder) Analog Ground Supply (Analog Input Stage) (Analog Decoder) 1.8 V Digital Voltage Supply (Digital Core) (Analog Decoder) Digital Ground Supply (Digital Core) (Analog Decoder) Digital Ground Supply (Digital Core) (Analog Decoder) Digital Ground Supply (Digital Core) (Analog Decoder) 3.3 V Digital Voltage Supply for Pins (Digital Core) (Analog Decoder) Digital Ground Supply for Pins (Analog Decoder) Digital Ground Supply (Digital Core) (Analog Decoder) Digital Ground Supply for Pins and Outputs (Output Stage) (Analog Decoder) 3.3 V Digital Voltage Supply for Pins (Output Stage) (Analog Decoder) 1.8 V Digital Voltage Supply (Output Stage) (Analog Decoder) Digital Ground Supply for Pins and Outputs (Output Stage) (Analog Decoder) Ground for Analog Decoder 3.3 V Analog Voltage Supply for A/ D Converter Analog Ground Supply for ADC 1.8 V Analog Voltage Supply for PLL IOs Analog Ground Supply for PLL IOs 1.8 V Analog Voltage Supply for PLL 3 Analog Ground Supply for PLL 3 1.8 V Analog Voltage Supply for PLL 2 Analog Ground Supply for PLL 2 1.8 V Analog Voltage Supply for PLL Analog Ground Supply for PLL
Type Output
PWR
L15
GND_CVBS
PWR
R14, R15, R16, T14, T15, T16 VDD18_CORE A12 A15 A20 N16, P16 B10 B22 B3 VSS VSS VSS VDD33_IO PWR PWR PWR PWR PWR
VSS_IO VSS VSS_IO
PWR PWR PWR
P23, N23 AA12, AA13 C17
VDD33_IO
PWR
VDD18_OUT VSS_OUT
PWR PWR
AB26, AC19, AD22, AD26, AD4, AE1, AE16, AE9, AF12, AF5 VSS PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Power Supply (Video Display Tv System, Analog Power Supplies) P6 N14 M6 N15 N6 M16 N6 N13 L6 P14 VCC33_ADC GND_ADC VCC18_IO GND_IO VCC18_PLL3 GND_PLL3 VCC18_PLL2 GND_PLL2 VDD18_PLL VSS_PLL
25/32
STD0550
Table 2: Pins sorted by function
Ball Connections
Alternate Function Ball Ball Name Main Function Input
Power Supply (Video Display TV System, Digital Power Supplies) Y6, AA6, AA7, AA8, AA9, AA10, AA11, T11, R11, P11, N11, T12, R12, P12, N12, T13, R13, P13 VDD33_IO R6, T6, U6, V6, W6 VDD18_CORE Power Supply Ground N1, AA1, AE1, P2, B3, Y3, D4, J4, N4, AD4, C6, F6, G6, H6, J6, F7, G7, H7, J7, K7, L7, M7, N7, P7, R7, T7, U7, V7, W7, Y7, D8, F8, G8, Y8, F9, G9, Y9, AE9, B10, F10, G10, Y10, F11, G11, Y11, A12, F12, G12, H12, Y12, AF12, F13, G13, L13, M13, N13, Y13, F14, G14, L14, M14, N14, P14, Y14, A15, F15, G15, L15, M15, N15, P15, Y15, F16, G16, L16, M16, Y16, AE16, C17, F17, G17, Y17, AB17, F18, G18, Y18, F19, G19, Y19, AC19, A20, F20, G20, H20, J20, K20, L20, M20, N20, P20, R20, T20, U20, V20, W20, Y20, AA20, AB20, F21, G21, H21, J21, K21, L21, M21, N21, W21, Y21, AA21, AB21, B22, L22, M22, N22, P22, R22, T22, AD22, T24, W24, D25, AA25, P26, AD26 VSS Supply Ground PWR 1.8 V Digital Voltage Supply PWR 3.3 V Digital Voltage Supply PWR
Type Output
1. The PIO must be configured in open drain. 2. Tie low whenever JTAG is not used. 3. All other outputs are synchronous to the rising or falling edge of the output pixel clock according to programming.
26/32
Ball Connections
STD0550
Table 3: Ballout Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
CPU _AD R17
CPU _DAT A11
CPU _DAT A12
CPU _DAT A15
CPU _PR OCL K
CPU _AD R10
CPU _AD R6
CPU _DAT A6
CPU _DAT A2
CPU _BE0
CPU _CA S1
GND
CPU _AD R4
SMI_ DQM U
GND
SMI_ DATA 14
SMI_ ADR 11
SMI_ ADR 8
SMI_ RAS
GND
SMI_ DATA 4
SMI_ DATA 0
SMI_ ADR 13
SMI_ ADR 1
SMI_ ADR 3
SPDI F_O UT
A
B
CPU _OE
CPU _DAT A10
GND
CPU _DAT A14
CPU _BE1
CPU _AD R12
CPU _AD R7
CPU _DAT A7
CPU _DAT A3
GND
CPU _CE0
CPU _AD R11
CPU _AD R3
SMI_ DATA 8
SMI_ DATA 11
SMI_ DATA 15
SMI_ ADR 9
SMI_ ADR 6
SMI_ CAS
SMI_ DATA 7
SMI_ DATA 3
GND
SMI_ ADR 10
SMI_ ADR 2
DAC _IRC LK
DAC _PC MCL K
B
C
CPU _AD R21
CPU _AD R20
CPU _AD R14
CPU _DAT A13
CPU _DAT A9
GND
CPU _AD R9
CPU _AD R5
CPU _DAT A5
CPU _DAT A1
CPU _RW
CPU _AD R15
CPU _AD R1
SMI_ DATA 10
SMI_ DATA 13
SMI_ CLK OUT
GND
SMI_ ADR 4
SMI_ DQM L
SMI_ DATA 5
SMI_ DATA 1
SMI_ ADR 12
SMI_ ADR 0
D_P CMO UT2
D_P CMO UT1
D_P CMO UT0
C
D
CPU _AD R18
CPU _AD R19
PIO0 _0
GND
CPU _DAT A8
CPU _AD R13
CPU _AD R8
GND
CPU _DAT A4
CPU _DAT A0
CPU _CA S0
CPU _AD R16
CPU _AD R2
SMI_ DATA 9
SMI_ DATA 12
SMI_ CLKI N
SMI_ ADR 7
SMI_ ADR 5
SMI_ WE
SMI_ DATA 6
SMI_ DATA 2
SMI_ CS0
SMI_ CS1
DAC _SCL K
GND
YCR CB0
D
E
CPU _WAI T
CPU _CE2
CPU _CE3
CPU _CE1
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 33
VDD 18
VDD 18
VDD 18
VDD 18
VDD _PLL
VDD 18
VDD 18
VDD 18
YCR CB_1 _PAD
YCR CB1
PIO4 _0
YCR CB_0 _PAD
E
F
PIO0 _6
PIO2 _6
CPU _RA S1
PIO2 _5
VDD 33
ND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD 18
PIO4 _1
PIO4 _2
YCR CB_2 _PAD
YCR CB2
F
G
PIO0 _2
DCU _TRI GOU T
PIO0 _7
PIO1 _2
VDD 33
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD 18
YCR CB_3 _PAD
YCR CB_4 _PAD
YCR CB4
YCR CB5
G
H
PIO2 _4
PIO2 _3
PIO2 _0
PIO2 _2
VDD 33
GND
GND
GND
GND
VDD _PC M
PIO4 _3
PIO4 _4
PIO4 _5
YCR CB_5 _PAD
H
J
IRQ1
IRQ0
PIO5 _2
GND
VDD 33
GND
GND
GND
GND
VDD _PC M
YCR CB3
YCR CB6
YCR CB_7 _PAD
YCR CB7
J
K
PIO3 _2
PIO3 _1
IRQ2
PIO3 _0
P_VI DEO 00
VDD 18_I O
GND
GND
GND
VDD _RG B
PIO4 _6
YCR CB_6 _PAD
PIO4 _7
CLK_ DATA
K
L
PIO3 _6
PIO3 _5
PIO3 _3
PIO3 _4
P_VI DEO 01
VDD 18_P LL1
GND
VDD 18_C ORE
VDD 18_C ORE
GND
GND
GND
GND
GND
GND
VDD _YC C
PWM 1
HSY NC
PIO2 _7
CLK_ DAT
L
M
BFLA G
BCL K
PIO3 _7
B_da ta
P_VI DEO 02
VCC 18_I O
GND
VDD 18_C ORE
GND
GND
GND
GND
GND
GND
GND
GND
PWM 2
PWM 0
PIO5 _3
PIO5 _4
M
N
GND
XTAL OUT
BSY NC
GND
P_VI DEO 03
VCC 18_P LL3
GND
VDD 33_I O
VDD 33_I O
GND
GND
GND
VDD 33IO
GND
GND
GND
PIX_ CLK
VSY NC
FIEL D
PIO5 _5
N
P
XTAL IN
GND
RES ET
TRS T
P_VI DEO 04
VCC 33_A DC
GND
VDD 33_I O
VDD 33_I O
VDD 33_I O
GND
GND
VDD 33IO
GND
VCC 18CV BS
GND
V_R EF_Y CC
CV_ OUT
I_RE F_YC C
GND
P
R
TDO
TDI
TMS
TCK
P_VI DEO 05
VDD 18_C ORE
GND
VDD 33_I O
VDD 33_I O
VDD 33_I O
VDD 18C ORE
VDD 18C ORE
VDD 18C ORE
GND
VCC 18CV BS
GND
I_RE F_R GB
V_R EF_R GB
Y_O UT
C_O UT
R
T
DCU _TRI G_IN
AUXCLK
PIO1 _4
POR TA4
P_VI DEO 06
VDD 18_C ORE
GND
VDD 33_I O
VDD 33_I O
VDD 33_I O
VDD 18C ORE
VDD 18C ORE
VDD 18C ORE
GND
VCC 18CV BS
GND
B_O UT
GND
G_O UT
R_O UT
T
U
PIO1 _0
PIO1 _1
PIO1 _3
POR TA5
P_VI DEO 07
VDD 18_C ORE
GND
GND
REF P_C VBS
NC
NC
CVB S1_Y
CVB S2_Y
C
U
V
PIO5 _0
PIO5 _1
PIO0 _3
POR TA7
P_VI DEO 08
VDD 18_C ORE
GND
GND
VCC 33_I O
NC
NC
B_C B
VIDE O_C OM
VIDE O_O UT
V
W
PIO2 _1
PIO1 _5
PIO0 _4
POR TA6
P_VI DEO 09
VDD 18_C ORE
GND
GND
GND
I2CA DDR
FB
GND
R_C R
ADCIN
W
Y
PIO0 _5
PIO0 _1
GND
P_VI DEO 10
P_VI DEO 11
VDD 33_I O
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TST_ MOD E
CLK XTM
CLK XTM
CLK SEL
G
Y
AA
GND
POR TC3
SCL
POR TC2
P_VI DEO 12
VDD 33_I O
VDD 33_I O
VDD 33_I O
VDD 33_I O
VDD 33_I O
VDD 33_I O
VDD 18O UT
VDD 18O UT
VDD 33_O UT
VCC 33SU B
VCC 18SU B
VCC 18SU B
VCC 18CL K
REF P_R GB
GND
GND
XTAL OUT
XTAL IN_C LKXT P
CLK XTP
GND
VSY NC
AA
AB
POR TC1
POR TC0
SDA
P_VI DEO 13
P_VI DEO 14
P_VI DEO 19
P_VI DEO 20
P_VI DEO 21
P_VI DEO 22
P_VI DEO 23
P_VI DEO 24
P_VI DEO 25
P_VI DEO 26
P_VI DEO 27
P_VI DEO 28
P_VI DEO 29
GND
NC
REF M_R GB
GND
GND
NRE SET
TCK
TDI
TMS
HSY NC
AB
AC
POR TA0
POR TD4
PLL_ LOC K
POR TA1
P_VI DEO 15
HOU T
POR TC5
POR TD2
POR TA3
SDR AM_ D13
SDR AM_ D9
ADD R_6
ADD R_9
NOT _BE1
NOT _RA S
ADD R_16
ADD R_2
SDR AM_ D5
GND
FLAS H_D1 4
FLAS H_D1 0
ADD R_14
NOT _CS_ FL
TRS T
NRE SET
TDO
AC
AD
POR TD7
POR TB4
POR TB1
GND
P_VI DEO 16
VOU T
POR TC6
POR TD1
POR TA2
SDR AM_ D14
SDR AM_ D10
ADD R_5
ADD R_8
NOT _BE0
NOT _CS_ SDR
ADD R_10
ADD R_3
SDR AM_ D4
SDR AM_ D1
FLAS H_D1 3
FLAS H_D9
GND
ADD R_18
FLAS H_D5
FLAS H_D2
GND
AD
AE
GND
POR TB3
POR TB0
DCL K
P_VI DEO 17
CLK_ DFL
POR TC4
POR TD3
GND
SDR AM_ D12
SDR AM_ D8
ADD R_7
ADD R_11
CKO UT_S DR
NOT _CA S
GND
ADD R_1
SDR AM_ D6
SDR AM_ D2
FLAS H_D1 5
FLAS H_D1 1
ADD R_19
ADD R_17
FLAS H_D6
FLAS H_D3
FLAS H_D0
AE
AF
POR TB5
POR TB2
POR TD5
DE
P_VI DEO 18
POR TC7
POR TD0
POR TD6
SDR AM_ D15
SDR AM_ D11
ADD R_4
GND
ADD R_12
CKIN _SD RAM
RD_ NOT WR
ADD R_15
ADD R_0
SDR AM_ D7
SDR AM_ D3
SDR AM_ D0
FLAS H_D1 2
FLAS H_D8
ADD R_13
FLAS H_D7
FLAS H_D4
FLAS H_D1
AF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
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STD0550
Detailed Description
3
Detailed Description
For more detailed description, refer to the standalone product datasheets:
STV2310, Revision 2.4, Jan. 2003: Multistandard TV/VCR Digital Video Decoder and Output Scaler. STV3550, Revision 1.2, Jan. 2004: Integrated Up-Converter with 32 bit CPU Core with Video Enhacers and Bitmap On-Screen Display. STD0100, Revision 1.0, Dec. 2003: MPEG Audio and Video Decoder.
4
Product Order Codes

STD0550Z: Standard product; Dolby Digital and Macrovision Encoding not active. STD0550ZD: Dolby Digital (AC3) active. STD0550ZM: Macrovision Encoding active. STD0550ZDM: Dolby Digital and Macrovision Encoding active.
28/32
General Package Information
STD0550
5
5.1
General Package Information
Package Mechanical Data
Figure 8: 532-Ball Plastic Ball Grid Array Package with 36 Center Ball Option
29/32
STD0550
Table 4: PBGA420 Dimensions DATABOOK (mm) Dim. Min.
A A1 A2 b D D1 E E1 e F .ddd .eee
1
General Package Information
DRAWING (mm) Max.
2.600
Typ.
Min.
0.500
Typ
Max
2.600 0.700 1.900
0.360 1.900 0.600 34.800 34.800 0.750 35.000 31.750 35.000 31.750 1.270 1.625 0.200 0.150 0.075 35.200 0.900 35.200
1.630 0.600 34.800 34.800 0.750 35.000 31.750 35.000 31.750 1.270 1.625
0.900 35.200 35.200
0.200 0.150 0.075
.fff2
1. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 2. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones.
30/32
Summary Of Changes
STD0550
6
Rev. 0.1 0.2 1.0
Summary Of Changes
Main Changes First Draft. Changes to Figure 1: STD0550 Block Diagram on page 4. Added ball list and ball configuration. Added Chapter 4: Product Order Codes on page 28. Date November 2003 February 2004 February 2004
31/32
STD0550
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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